The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (RC). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 1019 cm-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.