Eric Guiot

SOITEC
  • May 02, 2019 // 3:40pm – 4:30pm

    18.16 Innovative relaxed InGaN engineered substrates for red-green-blue µLEDs applications

    Eric Guiot, SOITEC
    Olvier ledoux, SOITEC S.A
    david sotta, SOITEC S.A
    Amélie DUSSAIGNE, CEA-LETI, Univ. Grenoble Alpes
    Benjamin DAMILANO, Université Côte d’Azur, CNRS, CRHEA
    Sébastien CHENOT, Université Côte d’Azur, CNRS, CRHEA
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  • 5.4 InP Based Engineered Substrates for Photonics and RF Applications

    Eric Guiot, SOITEC
    Alexis Drouin, SOITEC
    Olivier Ledoux, SOITEC S.A.
    Muriel Martinez, SOITEC S.A.
    Catherine Cadieux, Univ. Grenoble Alpes
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  • 7.5 Innovative GaN based engineered substrates for power applications

    Eric Guiot, SOITEC
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  • 5b.2 InP based engineered substrates for CPV cells above 46% of efficiency

    Eric Guiot, SOITEC
    Frank Dimroth, Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstrasse 2, 79110 Freiburg, Germany
    Alexis Drouin, SOITEC
    Charlotte Drazek
    Agnès de Buttet
    Thomas Tibbits
    Paul Beutel
    Christian Karcher
    Eduard Oliva
    Gerald Siefer
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  • May 12, 2022 // 3:20pm

    18.18 Reduction in Thermal Boundary Conductance of Annealed Direct Wafer Bonded GaN|Si Heterojunction Interfaces

    K. Huynh, University of California, Los Angeles
    M. E. Liao, University of California, Los Angeles, CA USA
    V. Dragoi, EV Group
    Eric Guiot, SOITEC
    Raphael Caulmilone, SOITEC
    M.S. Goorsky, University of California, Los Angeles
    X. Yan, University of California Irvine
    T. Pfeifer, University of Virginia Charlottesville
    N. Razek, EV Group and R-Ray Medical
    X. Pan, Soitec
    P. E. Hopkin, University of Virginia Charlottesville
    J. Tomko, University of Virginia Charlottesville

    Student Presentation

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  • 6.1.3.2024 SmartSiC™ 150 & 200mm engineered substrate: increasing SiC power device current density up to 30%

    Eric Guiot, SOITEC
    Frédéric Allibert, SOITEC
    Jürgen Leib, Fraunhofer IISB
    Tom Becker, Fraunhofer IISB
    Oleg Rusch, Fraunhofer IISB
    Alexis Drouin, SOITEC
    Walter Schwarzenbach, SOITEC

    6.1.3.2024 SmartSiC™ 150 & 200mm engineered substrate

  • 7A.4 – SmartSiC™ 150 & 200mm Engineered Substrate: Solving SiC Power Devices Bipolar Degradation

    Eric Guiot, SOITEC
    Frédéric Allibert, SOITEC
    Jürgen Leib, Fraunhofer IISB
    Tom Becker, Fraunhofer IISB
    R. Bagchi, Fraunhofer IISB
    G. Gelineau, University of Grenoble Alpes
    S. Barbet, University Grenoble Alpes
    R. Lavieville, University of Grenoble Alpes
    P. Godignon, University of Grenoble Alpes
    Walter Schwarzenbach, SOITEC

    7A.4 Final.2025

    Abstract
    The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.