Frédéric Allibert
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6.1.3.2024 SmartSiC™ 150 & 200mm engineered substrate: increasing SiC power device current density up to 30%
Eric Guiot, SOITECFrédéric Allibert, SOITECJürgen Leib, Fraunhofer IISBTom Becker, Fraunhofer IISBOleg Rusch, Fraunhofer IISBAlexis Drouin, SOITECWalter Schwarzenbach, SOITEC -
7A.4 – SmartSiC™ 150 & 200mm Engineered Substrate: Solving SiC Power Devices Bipolar Degradation
Eric Guiot, SOITECFrédéric Allibert, SOITECJürgen Leib, Fraunhofer IISBTom Becker, Fraunhofer IISBR. Bagchi, Fraunhofer IISBG. Gelineau, University of Grenoble AlpesS. Barbet, University Grenoble AlpesR. Lavieville, University of Grenoble AlpesP. Godignon, University of Grenoble AlpesWalter Schwarzenbach, SOITECAbstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.