Walter Schwarzenbach

SOITEC
  • Advanced Semiconductor on Insulator Substrates for Low Power and High Performance Digital CMOS Applications

    Bich-Yen Nguyen, SOITEC
    Mariam Sadaka, SOITEC
    Nicolas Daval, SOITEC
    Walter Schwarzenbach, SOITEC
    Cecile Aulnette, SOITEC
    Konstantin Bourdelle, SOITEC
    Fabrice Letertre, SOITEC
    Christophe Maleville, SOITEC
    Carlos Mazure, SOITEC
  • 8a.1 Beyond Silicon CMOS: Progress and Challenges

    Bich-Yen Nguyen, SOITEC
    Qweltaz Gaudin
    Mariam Sadaka, SOITEC
    Christophe Maleville, SOITEC
    Walter Schwarzenbach, SOITEC
    Konstantin Boudelle
    Christophe Figuet
    Download Paper
  • 6.1.3.2024 SmartSiC™ 150 & 200mm engineered substrate: increasing SiC power device current density up to 30%

    Eric Guiot, SOITEC
    Frédéric Allibert, SOITEC
    Jürgen Leib, Fraunhofer IISB
    Tom Becker, Fraunhofer IISB
    Oleg Rusch, Fraunhofer IISB
    Alexis Drouin, SOITEC
    Walter Schwarzenbach, SOITEC

    6.1.3.2024 SmartSiC™ 150 & 200mm engineered substrate

  • 7A.4 – SmartSiC™ 150 & 200mm Engineered Substrate: Solving SiC Power Devices Bipolar Degradation

    Eric Guiot, SOITEC
    Frédéric Allibert, SOITEC
    Jürgen Leib, Fraunhofer IISB
    Tom Becker, Fraunhofer IISB
    R. Bagchi, Fraunhofer IISB
    G. Gelineau, University of Grenoble Alpes
    S. Barbet, University Grenoble Alpes
    R. Lavieville, University of Grenoble Alpes
    P. Godignon, University of Grenoble Alpes
    Walter Schwarzenbach, SOITEC

    7A.4 Final.2025

    Abstract
    The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.