Walter Schwarzenbach

SOITEC

  • Advanced Semiconductor on Insulator Substrates for Low Power and High Performance Digital CMOS Applications

    Bich-Yen Nguyen, SOITEC
    Mariam Sadaka, SOITEC
    Nicolas Daval, SOITEC
    Walter Schwarzenbach, SOITEC
    Cecile Aulnette, SOITEC
    Konstantin Bourdelle, SOITEC
    Fabrice Letertre, SOITEC
    Christophe Maleville, SOITEC
    Carlos Mazure, SOITEC

  • 8a.1 Beyond Silicon CMOS: Progress and Challenges

    Bich-Yen Nguyen, SOITEC
    Qweltaz Gaudin
    Mariam Sadaka, SOITEC
    Christophe Maleville, SOITEC
    Walter Schwarzenbach, SOITEC
    Konstantin Boudelle
    Christophe Figuet
    Download Paper

  • 6.1.3.2024 SmartSiC™ 150 & 200mm engineered substrate: increasing SiC power device current density up to 30%

    Eric Guiot, SOITEC
    Frédéric Allibert, SOITEC
    Jürgen Leib, Fraunhofer IISB
    Tom Becker, Fraunhofer IISB
    Oleg Rusch, Fraunhofer IISB
    Alexis Drouin, SOITEC
    Walter Schwarzenbach, SOITEC

    [embeddoc url=”https://csmantech.org/wp-content/uploads/2024/06/6.1.3.2024-SmartSiC™-150-200mm-engineered-substrate.pdf” download=”all”]