In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

10B.2 Final.2025

Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD(Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky diode manufacturing process and is compared to final wafer level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on indie depletion voltage values, allowing for a direct comparison with final electrical device performance. Micro-scale, QUAD and voltage data within each individual diode can gain further insight into the electrical nature of the defects causing the device failure. The results demonstrate a strong correlation between the inline QUAD bin map results and final device electrical properties, highlighting the potential of QUAD as a practical and powerful inline tool. This technique offers a complementary approach to UVPL defect imaging, identifying electrically active defects and enhancing estimations of the final production yield.