M.A. Mastro

U.S. Naval Research Laboratory

  • 10.5.2023 Accuracy of Machine Learning Models on Predicting the Properties of Vertical GaN Diodes

    James Gallagher, U.S. Naval Research Laboratory
    Michael A. Mastro, U.S. Naval Research Laboratory
    Mona Ebrish, Vanderbilt University, Nashville, TN
    Alan Jacobs, U.S. Naval Research Laboratory
    Brendan. P. Gunning, Sandia National Labs, Albuquerque, NM
    Robert Kaplar, Sandia National Labs, Albuquerque, NM

    10.5.2023_Gallagher

  • 3B.5 – Stability of 3.3 kV Planar GaN Diodes with Nitrogen Implanted Termination under High Temperature Reverse Bias Stressing

    Alan Jacobs, U.S. Naval Research Laboratory
    James Spencer Lundh, National Research Council Postdoctoral Fellow, Residing at NRL
    Travis J. Anderson, U.S. Naval Research Laboratory
    Geoffrey M. Foster, U.S. Naval Research Laboratory
    Andrew Koehler, U. S. Naval Research Laboratory
    J. C. Gallagher, U.S. Naval Research Laboratory
    Brendan. P. Gunning, Sandia National Labs, Albuquerque, NM
    Robert Kaplar, Sandia National Labs, Albuquerque, NM
    Karl D. Hobart, U.S. Naval Research Laboratory
    M.A. Mastro, U.S. Naval Research Laboratory

    3B.5 Final.2025

    ABSTRACT
    Planar vertical gallium nitride devices are capable of utilizing the beneficial material properties inherent to bulk GaN without the interference of surface leakage pathways or passivation failures inherent to lateral devices, however, the stability and long-term viability of implanted termination necessitates study. Here we show  stressing of 3.3kV vertical GaN diodes with nitrogen implanted termination at over 80% of the breakdown voltage and at up to 200°C for over 400 hours. Some diodes exhibit a burn-in effect with small changes to the breakdown voltage and leakage at breakdown while others exhibit robust and nearly invariant behavior to the limits of testing. Additionally, thermal stressing of a cohort of devices without bias shows an increased degradation of breakdown voltage above 300°C and differentiation of devices within the cohort beyond 350°C enabling further study of the degradation mechanisms.

  • 4B.4 – Double-Side Diamond Cooling of GaN HEMTs and Progress Towards Further Reductions in Junction-to-Package Thermal Resistance

    James Spencer Lundh, National Research Council Postdoctoral Fellow, Residing at NRL
    F. Vasquez, University of Connecticut
    A. J. Cruz Arzon, University of Connecticut
    T.I. Feygelson, U.S. Naval Research Laboratory, Washington DC
    Alan Jacobs, U.S. Naval Research Laboratory
    Andrew Koehler, U. S. Naval Research Laboratory
    B.B. Pate, U.S. Naval Research Laboratory
    Karl D. Hobart, U.S. Naval Research Laboratory
    Travis J. Anderson, U.S. Naval Research Laboratory
    M.A. Mastro, U.S. Naval Research Laboratory
    G. Pavlidis, University of Connecticut
    D. Francis
    M.J. Tadjer, U.S. Naval Research Laboratory

    4B.4 Final.2025

    Abstract
    Herein, we demonstrate top, bottom, and double-side thermal management strategies for gallium nitride (GaN) high electron mobility transistors (HEMTs). The cooling technologies investigated include GaN/SiC (reference), GaN/diamond (bottom-side), diamond/GaN/SiC (top-side), and diamond/GaN/diamond (double-side). We review processing methods to realize these device structures as well as the intricacies of the fabrication process. From DC output characteristics, the diamond/GaN/diamond HEMTs demonstrate over 0.6 A/mm at VGS = 2 V. From a thermal perspective, the double-side diamond cooling approach enabled operation at DC power densities of ~30 W/mm with a peak temperature rise of ~50 K at the drain-side edge of the gate electrode. Finally, we demonstrate our initial efforts towards diamond encasement of AlGaN/GaN epilayers to further reduce device-level thermal resistance.

  • 10B.1 – Mapping Defects in SiC Wafers Using a Multi-Channel Convolutional Neural Network

    James Gallagher, U.S. Naval Research Laboratory
    N. Mahadik, U.S. Naval Research Laboratory
    R. E. Stahlbush, U.S. Naval Research Laboratory
    Karl D. Hobart, U.S. Naval Research Laboratory
    M.A. Mastro, U.S. Naval Research Laboratory

    10B.1 Final.2025

    Abstract
    Though wide bandgap semiconductors offer superior performance to its Si based counterpart, the current state of the art manufacturing technology produces several defects preventing devices from performing optimally. Particularly in SiC, the methods for detecting extended defects such as threading edge dislocations (TED), threading screw dislocations (TSD), basel plane dislocations (BPD), stacking faults, and polytype inclusions are well established; however, automated quantitative analysis is challenging due to the variable size, shape, and intensity of these numerous defects. This study focuses on developing machine learning models using multiple measurements with different techniques including x-ray topography (XRT) and ultraviolet photoluminescence (UVPL) to locate and quantify the microscopic defects on a macroscopic scale.