Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min^-1.

3.1.4.2024 Plasma Dicing for High Yield SiC Singulation

2A.4 Final.2025

Abstract

Vertical GaN MOSFETs are a promising technology for next generation efficient power systems. Here we investigate the effect of operating temperature on the on-state performance of quasi-vertical GaN MOSFETs, fabricated on SiC substrates. The threshold voltage, transconductance and on-resistance were extracted from measured characteristics across a range of temperatures. Shifts in both threshold voltage and transconductance are attributed to temperature dependent trapping-detrapping at the MOS interface. These are discussed in relation to series resistance contributions in the channel, drift layer and access resistances at the source and drain contacts.

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.