Fabrication techniques and experimental data are presented for 850 nm GaAs P-i-N photodiodes designed for 50 Gb/s optical links. Optimizations in the device structure and the selective dry etching process reduce dark current below 1pA. Responsivity is shown to be comparable to commercial devices with similar dimensions. And microwave measurement shows a highest bandwidth of above 30 GHz, indicating potential for 60 Gb/s operation. Data rate testing is performed with a VCSEL up to 50 Gb/s, showing clear eye diagrams.

14.4.2023 Wu

6.2.4.2024 Develop Automated Oxide-Aperture Size Measurement for GaAs VCSELs

8.2.4.2024 Thermal Stability Enhancement of P-Metals Ohmic Contact in Oxide-VCSELs

6B.4 Final.2025

ABSTRACT
In this work, we report the development of a high-precision fabrication process for microcavity VCSELs operating at cryogenic temperatures with oxide-aperture sizes below 3 μm. To address the critical challenge of controlling oxide-aperture size during wet oxidation, a novel hybrid etch mask combining SiNx and PR was introduced, enabling vertical mesa sidewall profiles with improved reliability and process uniformity. This approach enhances the accuracy of oxide formation, crucial for scaling down VCSEL apertures while maintaining thermal and optical performance. The fabricated Cryo-VCSEL with 1.7 m aperture demonstrates exceptional output power of 3.93 mW and modulation bandwidth exceeding 50 GHz at 2.9 K, with successful PAM-4 data transmission at 112 Gbps. The process yields minimal aperture variation (~ 0.5 μm IQR) across samples, ensuring suitability for parameter extraction and VCSEL array integration. These advancements establish a scalable fabrication platform for high-speed, cryogenic VCSELs, supporting future optical interconnects in quantum computing systems.

11B.5 Final.2025

Abstract
In this work, the effects of emitter ledging on DC and RF performance in sub-micron InP DHBTs are investigated. We have demonstrated that incorporating a 160-nm emitter ledge leads to an over 100% increase in DC current gain (β), rising from 16 to 34. This gain increase is primarily due to the suppression of emitter peripheral surface recombination. However, increased emitter ledge also leads to a reduction in device high frequency fT and fMAX performance due to increase in device transit time and extrinsic resistance. Trade-off between enhanced beta gain and degraded RF bandwidth needs to be further studied on the emitter ledge length.