Niels Posthuma

Imec

  • 7.5.2023 Improving the yield for GaN-on-Si HEMT devices for power applications

    D. Fahle, AIXTRON SE Germany
    C. Mauder, AIXTRON SE
    H. Hahn, AIXTRON SE
    Z. Gao, AIXTRON SE
    Niels Posthuma, Imec
    Stefaan Decoutere, Imec, Leuven, Belgium

    7.5.2023_Improving the yield for GaN-on-Si HEMT devices for power applications_extended_v2

  • 3A.5 – 1000-Hour HTRB Test on 1200 V Lateral HEMTs with Engineered p-GaN Gate

    S. Kumar, imec
    M. Borga, imec
    D. Cingu, imec
    K. Greens, imec
    A. Vohra, imec, Leuven, Belgium
    Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
    Niels Posthuma, Imec
    S. Decoutere, imec

    3A.5 Final.2025

    Abstract
    Lateral p-GaN gate-based power HEMTs are fabricated using a 9 μm thick GaN buffer on 200 mm GaN-on-QST® engineered substrates with a poly-AlN core, targeting 1200 V applications. The fabricated devices on engineered p-GaN gate on 9 μm thick GaN buffer show good ON/OFF state electrical characteristics and breakdown ~ 1800 V. The reliability of the fabricated p-GaN HEMTs were evaluated by a 1000-hour high temperature reverse bias (HTRB) stress test at 1200 V. No impact of HTRB stress was observed on electrical parameters and the devices yield a high pass rate.