• Process

    • High Performance In-situ Monitoring System for ICP Dry Etching

      Tomoya Sugahara, Samco Inc.
      Shin-ichi Motoyama
      Peter Wood, SAMCO Inc.
      Atsuki Maruno, Samco Inc.

      Laser interferometric spectra and plasma emission spectra are widely used to realize precise dry etching depth control of compound semiconductor devices. However, fixed wavelength light sources for the laser interferometric systems are limited to analyze end point detection signals. Our ICP dry etching systems such as the RIE-400iP, and RIE-800iP are equipped with a high-performance in-situ monitoring system that can analyze multiple wavelengths from the reflected light of Xe or Xe-Hg (or Halogen lamp). The system is also capable of detecting the variation of plasma emission intensity simultaneously. In this work, we present examples of applying the high-performance in-situ monitoring system to GaAs, InP, and GaN-based device structure etching, and discuss the possibility of highly accurate and stable etching depth control.

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    • AlGaN/GaN Ohmic Contact Investigation

      Kai-Sin Cho, WIN Semiconductors Corp.
      Chiao-Yi Tsai, WIN Semiconductors Corp.
      Szu-Ting Chen, WIN Semiconductors Corp.
      Cheng-Ju Lin, WIN Semiconductors Corp.
      Yi-Wei Lien, WIN Semiconductors Corp
      Wei-Chou Wang, WIN Semiconductors Corp

      To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti3AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti3AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

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    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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    • The Effect of Delay Between Pre-clean and Metal Deposition on the Forward Current Voltage Characteristics of Schottky Devices

      Eric Finchem, MACOM
      Debdas Pal, MACOM
      Lorain Ross, Skyworks Solutions, Inc.
      Sean Doonan, Skyworks Solutions, Inc.
      Edmund Burke, Skyworks Solutions, Inc.

      Schottky devices play an important role in modern electronics. The forward biased current-voltage characteristics of such devices are linear on a semi-logarithm scale at intermediate bias voltages. However, the curve deviates from linearity at higher voltage primarily due to series resistance. The applied forward voltage on the device is equal to the sum of the voltage drops across the (1) junction, (2) series resistance, (3) depletion layer and (4) any parasitic resistive layer between the Schottky metal and the semiconductor. Therefore, the interface between the metal and the semiconductor plays an important role in determining the critical parameters of Schottky devices. In this investigation a controlled delay was introduced between the pre-metal clean and Schottky metal deposition steps of the fabrication process to study the effects of naturally grown oxide on the forward characteristics of the Schottky devices.  The results of the investigation indicate such delays cause significant increases in series resistance and ideality factor, as well as a decrease in barrier height.

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    • Fabrication of Recessed Structures for GaN HEMTs by a Simple Wet Etching Process

      Taketomo Sato, Hokkaido University
      Fumimasa Horikiri, Sciocs Company Limited
      Noboru Fukuhara, SCIOCS Company Ltd.
      Masachika Toguchi, Hokkaido University
      Kazuki Miwa, Hokkaido University
      Yoshinobu Narita, Sciocs Company Limited
      Osamu Ichikawa, SCIOCS Company Ltd.
      Ryota Isono, SCIOCS Company Ltd.
      Takeshi Tanaka, SCIOCS Company Ltd.

      Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K2S2O8 in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the Vth value was +0.4 V with a standard deviation of ±3.8 mV.

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    • Optimizing Bi-layer Lift-off Resist Processes for Insulator Films

      Lori Rattray, Kayaku Advanced Materials
      Robert Wadja, Kayaku Advanced Materials
      Dan Nawrocki, Kayaku Advanced Materials

      The bi-layer lift-off method has been used successfully to commercially fabricate many structures including source, drain ohmic contacts, gates and air bridges for use in Gallium Arsenide (GaAs), GaN, InP, MEMS and other semiconductor devices.  It is widely adopted for common pattern metallization processes.  The process utilizes LOR-PMGI (polydimethylglutarimide) plus an imaging resist to create a dual layer masking structure.  Uniquely, this structure can be customized because its composition and dimensions can be tailored for a given material-deposition-application system. This is enabling for use in select process applications.

      Deployment of VCSEL applications enabled by 5G latency advantages can benefit by using commercialized technology to comply industry development clockspeed.[1]  VCSEL devices can be broadly categorized in terms of deposition material thicknesses and structures based on power output.[2]  This study quantifies the most relevant bi-layer structural features for effective use with the reference metallization film, Aluminum.  It builds on these findings to explore the multivariate optimization required to successfully use bi-layer processing with common metal oxide insulators (SiO2 / Al2O3) in isotropically sputter deposited thicknesses of 100nm to 250nm.  A model is presented that characterizes the key variables.  Also, it introduces a new high temperature bi-layer process using a negative imaging resist capable of maintaining stability during higher temperature insulator deposition.  This investigation identifies the dimensional targets to fabricate successful bi-layer’s for use with sputtered insulators suitable for process optimization to facilitate evolving III-V applications.

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    • Study of new stepper solutions for various IoT devices

      Ken-Ichiro MORI, CANON INC.
      Noritoshi SAKAMOTO, CANON INC.
      Douglas SHELTON, CANON U.S.A. INC.
      Tomohiro OKAMOTO, CANON INC.
      Hiroyuki MIYAZAKI, CANON INC.

      To meet various process requirements from growing IoT devices, Canon has released FPA-3030iWa, FPA-3030i5+ and FPA-3030EX6 steppers based on the new FPA-3030 platform that is upgrade to the proven FPA-3000 stepper platform. In this paper, we will introduce FPA-3030iWa stepper solutions to support IoT device manufacturing and report evaluation data and advantages.

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    • Exploring the Challenges of Galiium Arsenide Plasma Dicing

      Owen Guy, Swansea University
      Will Worster, Swansea University
      Matthew Day, SPTS Technologies Limited
      M Jennings, KLA Corporation, SPTS Technologies Division, Swansea University
      Matt Elwin, Swansea University

      Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min-1.

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    • P-type and N-type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

      Takashi Kuroi, Nissin Ion Equipment Inc.
      Hrishikesh Das, ON Semiconductor USA
      Swapna Sunkari, ON Semiconductor USA
      Joshua Justice, ON Semiconductor USA
      Roman Malousek, ON Semiconductor CZ
      Jan Chochol, ON Semiconductor CZ
      Ryota Wada, Nissin Ion Equipment Inc.

      This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

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    • 100nm, Three-dimensional T-Gate for SLCFET Amplifiers

      Robert Howell, Northrop Grumman Corporation
      Annaliese Drechsler, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Corporation
      Kevin Frey, Northrop Grumman Corporation
      Monique Farrell, Northrop Grumman Corporation
      Georges Siddiqi, HRL Laboratories
      M. Scimonelli, Northrop Grumman (MS), Linthicum, MD
      Jordan Merkle, Northrop Grumman Corporation
      Josephine Chang, Northrop Grumman Corporation

      This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 107. This gate scaling allows the device to reach FT / FMAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

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    • Wet-etching Process Problem Identification in Type-II InP DHBT for 5G Power Application

      Milton Feng, University of Illinois Urbana-Champaign
      Yu-Ting Peng, University of Illinois at Urbana Champaign
      Xin Yu, University of Illinois at Urbana-Champaign

      Wet-etching issues in type-II DHBT process fabricated by standard triple-mesa wet-etching have been identified and reported in this paper. For comparison, devices fabricated by hybrid-etching with incorporation of inductively-coupled-plasma (ICP) are also present. With better uniformity and yield, hybrid-etching process can potentially lead to a more reliable and reproducible process for 5G power amplifier application.

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    • Development of Manufacturable Commercial 6-inch InP HBT

      Cheng-Kuo Lin, WIN Semiconductors Corp
      Yu-An Liao, WIN Semiconductors Corp.
      Chun-Wei Lin, WIN Semiconductors Corp.
      Jung-Hao Hsu, WIN Semiconductors Corp.
      Shu-Hsiao Tsai, WIN Semiconductors Corp

      A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

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    • Effective Polishing of Al-face of AlN Substrates using Advanced Polishing Process and Consumables

      Alicia Walters, Engis Corporation
      Artem Titov, Engis Corporation

      This paper presents a novel surface finishing process and consumables for achieving an epi-ready finish on the Al-face of Aluminum Nitride (AlN) single crystal substrates and wafers. The designed combination of process parameters and newly developed slurries produces superior surface finish on the Al-face of AlN substrates and high removal rates yielding in significant reduction of wafer surface finishing process times for stock removal and chemical-mechanical polishing (CMP) steps.

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    • CMP Pad Conditioning and Applications to Compound Semiconductor Wafer Processing

      Terry Knight, Eminess Technologies
      Andrew Lawing, Kinik North America
      William Gemmill, Eminess Technologies

      Pad conditioning is critical to maintaining the required process stability and performance in semiconductor CMP. As the process and performance requirements for substrate polishing in the compound semiconductor industry become more stringent, we believe there are significant opportunities for improvement via more extensive adoption of optimized pad conditioning protocols. In this paper we will review the pertinent state of the art in semiconductor CMP and propose some specific target areas for adoption in compound semiconductor substrate polishing.

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    • Impact of water content in NMP on ohmic contacts in GaN HEMT technologies

      Michael Hosch, United Monolithic Semiconductors
      Alexander Hugger, United Monolithic Semiconductors GmbH, Ulm
      Aleksandra Dlugolecka, United Monolithic Semiconductors GmbH, Ulm
      Hermann Stieglauer, United Monolithic Semiconductors Germany
      Raphael Ehrbrecht, United Monolithic Semiconductors GmbH, Ulm

      Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

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    • Defect Detection and Mitigation in Low Pressure PECVD Systems: Special Case of Nodule Formation in Densified SiNx Films.

      Jeremiah Sires, Skyworks Solutions, Inc.

      Extensive literature exists on  characterization of SiNx (silicon nitride) films based on C-V (Capacitance – Voltage) performance and hydrogenation of films, as well as the photoluminescent properties studied through various spectroscopy methodologies (Raman, SIMS and XPS).  However, few physical defect studies, particularly in low frequency PECVD (Plasma-Enhanced Chemical Vapor Deposition), can be found.  This study will discuss in detail the formation of nodules in densified N-rich (N/Si > 1.33) SiNx films deposited via LF PECVD on CZ polished Si substrates via the formation of K centers and resulting Si nanoclusters and surrounding nitrogen depletion zones within the film.  Additionally, three distinct defect mechanisms are isolated and procedures implemented to mitigate product exposure through detection methodology and determination of appropriate preventative hardware maintenance.

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    • Development and Testing of Sub 0.5-micron Features for Advanced Lift-Off Processes

      Phil Greene, Ferrotec Corporation
      Phillip Tyler, Veeco Instruments
      Jennifer Rieker, EMD Performance Materials

      Previous studies have shown the importance of selecting the correct photoresist, metallization method, resist remover, and tool to achieve a successful lift-off[1].  Improper selection of just one of the four can result in insufficient lift-off due to conformal metal coating of the photoresist, greater number of defects, lower throughput and a higher cost of ownership.  Feature sizes of 50 µm down to 0.5 µm were previously demonstrated and this paper will focus on feature sizes under 0.5 µm.  These size features are gaining more traction in metal lift-off processes for RF and power applications that require smaller features for improved performance.

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    • Effect of Process Variation on Pinch-Off Voltage of Depletion-Mode pHEMT

      Fred Pool, Qorvo
      Jinhong Yang, Qorvo
      Chang’e Weng, Qorvo
      Kaushik Vaidyanathan, Qorvo
      Moreen Minkoff, Qorvo
      Matthew Porter, Qorvo, Inc
      Michele Wilson, Qorvo
      Tertius River, Qorvo
      Mark Tesauro, Qorvo

      Pinch-off voltage is a key device characteristic of depletion-mode pseudomorphic high electron mobility transistors (pHEMT). Pinch-off voltage (Vp) shifts caused by manufacturing process variation were studied in this paper. Experimental results showed higher pinch-off voltage if the AlGaAs Schottky layer is oxidized or contaminated by metal. A significant increase in pinch-off voltage was observed when the Schottky layer was exposed to air for up to 2 hours after oxygen plasma treatment.  Investigation also revealed an increase in pinch-off voltage in relation to staging time and environment before gate contact metal deposition. In both cases, the effective thickness of the AlGaAs Schottky layer was reduced, and pinch-off voltage was increased. Models of metal cross-contamination and a “last wafer” effect in wet clean processing were also evaluated to address pinch-off voltage variation.

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    • A Study of Low-Annealing-Temperature Ohmic Contact on n-Type GaN Layers

      Shyh-Chiang Shen, Georgia Institute of Technology
      Minkyu Cho, Georgia Institute of Technology, Atlanta, GA
      Marzieh Bakhtiary Noodeh, Georgia Institute of Technology, Atlanta, GA
      Theeradetch Detchprohm, Georgia Institute of Technology
      Russell Dupuis, Georgia Tech
      Barry Wu, Keysight Technologies, Inc.
      Don D’Avanzo, Keysight Technologies, Inc.

      Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (rc,sp) in the mid-E-6 Ω∙cm2 range.  The rc,sp was further reduced to  6.8E-7 Ω∙cm2 after an annealing step at 600 oC.

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    • Reducing Lens Heating Effects on High Mileage Projection Lenses Used in Optical Lithography

      Steven Mayer, Skyworks Solutions, Inc

      The demand for low cost lithography solutions in modern manufacturing has led to extended lifetime of optical lithography equipment. Use of steppers with “high mileage” has shown that heating of the projection lens with high energy input severely degrades the aerial image. This paper discusses the lens heating effects and discusses the common solutions to address this issue. This paper also demonstrates a practical solution used in high volume manufacturing environment.
            This paper will discuss how absorption increases with the summation of energy through a projection lens and its effect on lens aberrations. Classical techniques to reduce lens heating effects will be presented. Low NA, low Sigma resist process, targeted for lift-off  applications, is used to study its effect on lens heating.   Solution for high transmittance, high dose application will be presented with theory, data and images.

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