9.3.2023_Treidel

4.1.4.2024 Wafer Bow Tuning with Stealth Laser Patterning for Vertical High Voltage Devices

2A.2 Final.2025

Abstract
In this study, vertical GaN trench MOSFETs were fabricated utilizing a novel gate dielectric composed of hafnium oxide (HfO₂) layered with aluminum oxide (Al₂O₃) to enhance device performance compared to those employing Al₂O₃ alone. The transistors incorporating the HfO₂ / Al₂O₃ layered gate dielectric exhibited up to three times increase in forward current, five times enhancement in gate breakdown voltage and significantly reduced threshold voltage shift induced by gate forward voltage stress, relative to devices with an Al₂O₃-only gate dielectric. Furthermore, the improved gate structure resulted in higher channel mobility (~11.1 cm²/Vs) and a reduced ON-state resistance (3.1 ± 0.6 mΩ·cm²).

3A.3 Final.2025

Abstract
In this study, we present vertical GaN based pn-diodes designed for high-voltage applications. These devices were initially grown and processed on 4-inch sapphire substrates and subsequently transferred to 4-inch tungsten substrates, enabling a fully vertical conduction path. Laser lift-off was employed to detach the GaN-membrane device structures from their original sapphire substrate. The diodes exhibit enhanced forward conduction following the transfer process, with the ON-state resistance decreasing from 1.52 ± 0.05 mΩcm2 to 1.15 ± 0.05 mΩcm2. During this time, the blocking strength remains largely unaffected, with its wafer level median value decreasing marginally from 1015 ± 47 V to 988 ± 57 V. The high device yields achieved through the membrane transfer procedure highlight the cost-competitiveness of this vertical GaN device technology for high-power applications, eliminating the need for expensive GaN substrates.

12.5 Final.2025

In this study, the reduction of contact resistance (Rc) in RF GaN HEMTs with an 8 nm Al₀.₃₆Ga₀.₆₄N barrier layer was investigated using two approaches: Si implantation and recess etching. Employing the Si implantation method with an optimized dopant activation procedure reduced Rc by 70% down to approximately 0.17 Ω·mm. In comparison, a reference alloyed Ti/Al/Ni/Au ohmic contact scheme without implantation achieved an Rc of ~0.60 Ω·mm. For the same epitaxial layer design, utilizing the recess etching technique reduced Rc by 50% down to 0.25 Ω·mm.