10.3.2023 Ostermay final

2A.2 Final.2025

Abstract
In this study, vertical GaN trench MOSFETs were fabricated utilizing a novel gate dielectric composed of hafnium oxide (HfO₂) layered with aluminum oxide (Al₂O₃) to enhance device performance compared to those employing Al₂O₃ alone. The transistors incorporating the HfO₂ / Al₂O₃ layered gate dielectric exhibited up to three times increase in forward current, five times enhancement in gate breakdown voltage and significantly reduced threshold voltage shift induced by gate forward voltage stress, relative to devices with an Al₂O₃-only gate dielectric. Furthermore, the improved gate structure resulted in higher channel mobility (~11.1 cm²/Vs) and a reduced ON-state resistance (3.1 ± 0.6 mΩ·cm²).

12.17 Final.2025

Abstract
For high-performance GaN-based transistors, minimizing contact resistance is essential to reduce power losses and enhance switching efficiency. Achieving highly- doped contact areas in GaN is challenging due to its high binding energy and self-compensation effects. This study investigates the electrical activation of silicon-implanted GaN-on-sapphire structures using rapid thermal annealing (RTA) and optimized cap layers. Various cap materials, including sputtered and PECVD SiNx, Al2O3, and bilayer approaches, were evaluated for their ability to prevent GaN decomposition during high-temperature annealing. The best-performing cap consisted of a 10 nm thick CVD SiNx layer followed by 10 nm ALD Al2O3 layer, providing effective surface protection up to 1300 °C. Sheet resistance measurements indicate that higher annealing temperatures and optimized spike annealing conditions improve dopant activation, with the lowest sheet resistance of 188 Ω/□ achieved at 1400 °C using a two-spike process. These findings provide insights into optimizing thermal processes for high-performance GaN device fabrication.