GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.
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Integration of GaN Power ICs on 200 mm Engineered Substrates
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March 10, 2022 // 8:45am
13.2 Propelling the Power Electronics Revolution: 200 mm Diameter, 100 V to 1800 V and Beyond GaN-on-QST® High Volume Device Manufacturing Platform
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6.1.1.2024 (Invited)Taking GaN to the Next Level of 100 V to 2000 V and Beyond Scalability with the Revolutionary 200 mm and 300 mm QST® Manufacturing Platform
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11.2.3.2024 Time-Dependent Conduction Mechanisms in Superlattice Layers on 200 mm Engineered Substrates
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3A.5 – 1000-Hour HTRB Test on 1200 V Lateral HEMTs with Engineered p-GaN Gate
Abstract
Lateral p-GaN gate-based power HEMTs are fabricated using a 9 μm thick GaN buffer on 200 mm GaN-on-QST® engineered substrates with a poly-AlN core, targeting 1200 V applications. The fabricated devices on engineered p-GaN gate on 9 μm thick GaN buffer show good ON/OFF state electrical characteristics and breakdown ~ 1800 V. The reliability of the fabricated p-GaN HEMTs were evaluated by a 1000-hour high temperature reverse bias (HTRB) stress test at 1200 V. No impact of HTRB stress was observed on electrical parameters and the devices yield a high pass rate.
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