11.4.2023_Masten- NCD HFET- 2023 CS Mantech – final paper_hnm
Bradford B. Pate
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Boron-Doped P Nanocrystalline Diamond Gate Electrode for AlGaN-GaN HEMTs
Marko J. Tadjer, U.S. Naval Research LaboratoryTatyana I. Feygelson, American Society for Engineering Education, United States Naval Research Lab. Universidad Politecnica de MadridJennifer K. Hite, Naval Research LaboratoryBradford B. Pate, U.S. Naval Research LaboratoryCharles R. Eddy, Naval Research LaboratoryJr., Naval Research LaboratoryFrancis J. Kub, Naval Research Laboratory -
Diamond-coated High Density Vias for Silicon Substrate-side Thermal Management of GaN HEMTs
Marko J. Tadjer, U.S. Naval Research LaboratoryTatyana I. Feygelson, American Society for Engineering Education, United States Naval Research Lab. Universidad Politecnica de MadridAshu Wang, American Society for Engineering Education, United States Naval Research Lab. Universidad Politecnica de MadridBradford B. Pate, U.S. Naval Research LaboratoryFritz J. Kub, U.S. Naval Research Laboratory -
11.4.2023 Nanocrystalline Diamond-Capped β-(AlxGa1-x)2O3/Ga2O3 Heterostructure FieldEffect Transistor
Hannah N. Masten, National Research Council Postdoctoral Fellow, Residing at NRLJames Spencer Lundh, National Research Council Postdoctoral Fellow, Residing at NRLTatyana Feygelson, U. S. Naval Research LaboratoryJoseph Spencer, U.S. Naval Research LaboratoryTatyana I. Feygelson, American Society for Engineering Education, United States Naval Research Lab. Universidad Politecnica de MadridJennifer K. Hite, Naval Research LaboratoryDaniel Pennachio, U.S. Naval Research Laboratory, Washington DCAlan Jacobs, U.S. Naval Research LaboratoryBoris Feygelson, U.S. Naval Research LaboratoryKohei Sasaki, Novel Crystal TechnologyAkito Kuramata, Novel Crystal Technology, IncPai-Ying Liao, Purdue UniversityPeide D. Ye, Purdue UniversityBradford Pate, Naval Research LaboratoryTravis J. Anderson, U.S. Naval Research LaboratoryMarko J. Tadjer, U.S. Naval Research Laboratory -
10.1.3.2024 3D Diamond Growth for GaN Cooling and TBR Reduction
Daniel Francis, Akash Systems, San Francisco, CA, USASai Charan Vanjari, University of BristolXiaoyang Ji, University of BristolTatyana Feygelson, U. S. Naval Research LaboratoryJoseph Spencer, U.S. Naval Research LaboratoryHannah N. Masten, National Research Council Postdoctoral Fellow, Residing at NRLAlan Jacobs, U.S. Naval Research LaboratoryJames Spencer Lundh, National Research Council Postdoctoral Fellow, Residing at NRLMarko Tadjer, U.S. Naval Research LaboratoryTravis J. Anderson, U.S. Naval Research LaboratoryKarl D. Hobart, U.S. Naval Research LaboratoryBradford Pate, Naval Research LaboratoryJames Pomeroy, University of BristolMatthew Smith, University of BristolMartin Kuball, University of BristolLoading...
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4B.4 – Double-Side Diamond Cooling of GaN HEMTs and Progress Towards Further Reductions in Junction-to-Package Thermal Resistance
James Spencer Lundh, National Research Council Postdoctoral Fellow, Residing at NRLF. Vasquez, University of ConnecticutA. J. Cruz Arzon, University of ConnecticutT.I. Feygelson, U.S. Naval Research Laboratory, Washington DCAlan Jacobs, U.S. Naval Research LaboratoryAndrew Koehler, U. S. Naval Research LaboratoryB.B. Pate, U.S. Naval Research LaboratoryKarl D. Hobart, U.S. Naval Research LaboratoryTravis J. Anderson, U.S. Naval Research LaboratoryM.A. Mastro, U.S. Naval Research LaboratoryG. Pavlidis, University of ConnecticutD. FrancisM.J. Tadjer, U.S. Naval Research LaboratoryAbstract
Herein, we demonstrate top, bottom, and double-side thermal management strategies for gallium nitride (GaN) high electron mobility transistors (HEMTs). The cooling technologies investigated include GaN/SiC (reference), GaN/diamond (bottom-side), diamond/GaN/SiC (top-side), and diamond/GaN/diamond (double-side). We review processing methods to realize these device structures as well as the intricacies of the fabrication process. From DC output characteristics, the diamond/GaN/diamond HEMTs demonstrate over 0.6 A/mm at VGS = 2 V. From a thermal perspective, the double-side diamond cooling approach enabled operation at DC power densities of ~30 W/mm with a peak temperature rise of ~50 K at the drain-side edge of the gate electrode. Finally, we demonstrate our initial efforts towards diamond encasement of AlGaN/GaN epilayers to further reduce device-level thermal resistance.